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ThinkMind // ADVCOMP 2016, The Tenth International Conference on Advanced Engineering Computing and Applications in Sciences // View article advcomp_2016_3_10_20004


Prototype Design of Computationally Efficient Digital Down Converter for 3G Applications

Authors:
Rajesh Mehra

Keywords: 3G Mobile Communication; Base Stations; Radio Transceivers; Reconfigurable Logic; Software Radio

Abstract:
This paper presents Digital Down Converter (DDC) design for Software Defined Radio (SDR) base stations using reconfigurable logic. A computationally efficient multistage design technique is used to achieve an efficient solution for third generation (3G) mobile communication. The proposed design is developed in three stages and each stage has been optimized using Park McClellan algorithm to minimize the filter order. This was further supplemented with computationally efficient polyphase decomposition technique. The Partially Serial Pipelined MAC algorithm is used to optimize both speed and area simultaneously. The embedded multipliers of target Field Programmable Gate Array (FPGA) are optimally utilized and efficiently mapped to enhance the system performance. The proposed DDC has shown an improvement of 19 % in speed with improved resource utilization to provide a computationally efficient and cost effective solution for SDR based wireless applications.

Pages: 52 to 57

Copyright: Copyright (c) IARIA, 2016

Publication date: October 9, 2016

Published in: conference

ISSN: 2308-4499

ISBN: 978-1-61208-506-7

Location: Venice, Italy

Dates: from October 9, 2016 to October 13, 2016

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