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ThinkMind // ALLSENSORS 2017, The Second International Conference on Advances in Sensors, Actuators, Metering and Sensing // View article allsensors_2017_1_10_70014


Design of a High-speed CMOS Image Sensor with an Intelligent Digital Correlated Double Sampling and a Symmetrical 3-Input Comparator

Authors:
Minhyun Jin
Daehyuck Kim
MIinkyu Song

Keywords: CMOS image sensor(CIS); one-ramp digital correlated double sampling; symmetrical 3-input comparator; subtraction algorithm.

Abstract:
In order to improve the frame rate of a CMOS image sensor (CIS), a novel technique of correlated double sampling (CDS) and a symmetrical 3-input comparator are discussed. In the conventional digital CDS, a subtraction algorithm between the reset digital code and the pixel digital code has been normally adopted. Thus, it needs two ramps and takes a much more operating time, compared to that of analog CDS. In this paper, an intelligent digital CDS is proposed drastically to reduce the operating time. Further, a symmetrical 3-input comparator to implement the intelligent digital CDS is also described. A high speed CIS with the proposed CDS and a symmetrical 3-input comparator has been fabricated with Samsung 0.13um CIS technology. A high frame rate of 240fps is achieved at the VGA resolution of 640x480 with 39mW power consumption.

Pages: 1 to 4

Copyright: Copyright (c) IARIA, 2017

Publication date: March 19, 2017

Published in: conference

ISSN: 2519-836X

ISBN: 978-1-61208-543-2

Location: Nice, France

Dates: from March 19, 2017 to March 23, 2017

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