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ThinkMind // CENICS 2015, The Eighth International Conference on Advances in Circuits, Electronics and Micro-electronics // View article cenics_2015_1_10_60030


An Efficient Spike Detection VLSI Architecture Based on Normalized Correlator

Authors:
Wen-Jyi Hwang
Chun-Fu Lin
Szu-Huai Wang

Keywords: Spike Sorting; Spike Detection; FPGA; Network on Chip

Abstract:
This paper aims to present an effective circuit for noisy spike detection. The circuit detects spikes by the normalized correlators. The operations of the correlators involve filtering, block energy computation, normalized correlation, and thresholding. All the computations are carried out in a pipelined fashion. The circuit has been implemented by the field programmable gate arrays (FPGAs). The circuit is used as a hardware accelerator in a network-on-chip (NOC) platform for performance evaluation. Experimental results reveal that the proposed circuit provide realtime computation for the noisy spike detection with high true postive and low false alarm rates.

Pages: 1 to 6

Copyright: Copyright (c) IARIA, 2015

Publication date: August 23, 2015

Published in: conference

ISSN: 2308-426X

ISBN: 978-1-61208-430-5

Location: Venice, Italy

Dates: from August 23, 2015 to August 28, 2015

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