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ThinkMind // GREEN 2018, The Third International Conference on Green Communications, Computing and Technologies // View article green_2018_1_20_80021


A Fast Heuristic for Tasks Assignment in Manycore Systems with Voltage-Frequency Islands

Authors:
Shervin Hajiamini
Behrooz Shirazi
Hongbo Dong

Keywords: Manycore System; Task Partitioning; Dynamic Voltage-Frequency Scaling; Voltage-Frequency Islands; Optimization Framework; Energy Efficiency

Abstract:
Dynamic Voltage/Frequency Scaling (DVFS) is a well-known technique that dynamically scales cores’ Voltage/Frequency (V/F) levels to save energy or minimize the application’s execution time in manycore systems. This paper proposes an optimization framework that provides a DVFS-based cost- and energy-efficient methodology to balance time-energy tradeoffs in manycore systems with Voltage/Frequency Island (VFI) architectures. The proposed methodology has two steps: 1) formulating a Mixed Integer Linear Programming (MILP) problem that populates islands through the task-to-island assignments given that the islands are symmetric, 2) formulating an Integer Linear Programming (ILP) problem that computes the V/F levels of cores in each island per execution phase of parallel applications. The first step, which is performed at compile-time, considers the per execution phase computational characteristics of the tasks for islanding while the second step optimizes the V/F levels of formed islands at runtime. As solutions time of the proposed task-to-island assignment problem increases significantly with a large number of tasks or islands, this paper presents a fast heuristic that only requires a sorting procedure in its most time-consuming step and obtains near-optimal solutions. The proposed framework’s energy efficiency is compared to an optimal, per-core islanding that establishes the best energy-time solutions for the experimented applications. Using Energy-Delay Product as performance metric, experimental results show that the framework’s energy efficiency, at the worst case, is within 13% of the per-core DVFS. The results also show that this framework utilizes the idle times of low Central Processing Unit (CPU)-intensive benchmarks to increase energy saving with reasonable performance loss.

Pages: 5 to 13

Copyright: Copyright (c) IARIA, 2018

Publication date: September 16, 2018

Published in: conference

ISSN: 2519-8483

ISBN: 978-1-61208-667-5

Location: Venice, Italy

Dates: from September 16, 2018 to September 20, 2018

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