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ThinkMind // ICWMC 2012, The Eighth International Conference on Wireless and Mobile Communications // View article icwmc_2012_11_50_20448


FPGA Implementation of CRC with Error Correction

Authors:
Wael El-Medany

Keywords: FPGA; CRC Code; IP Core; VLSI.

Abstract:
This paper presents a Cyclic Redundancy Check (CRC) soft core design and its hardware implementation on Field Programmable Gate Array (FPGA). The core design includes both of the Encoder and Decoder systems to be used for the serial data transmission and reception of the Wireless Transceiver System. VHDL (VHSIC Hardware Description Language) has been used for describing the hardware of the Intellectual Property (IP) core chip. The core design has been simulated using and tested using ISim (VHDL/Verilog). Spartan 3A FPGA starter kit from Xilinx has been used for downloading the design into Xilinx Spartan 3A FPGA chip.

Pages: 266 to 271

Copyright: Copyright (c) IARIA, 2012

Publication date: June 24, 2012

Published in: conference

ISSN: 2308-4219

ISBN: 978-1-61208-203-5

Location: Venice, Italy

Dates: from June 24, 2012 to June 29, 2012

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