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ThinkMind // VALID 2013, The Fifth International Conference on Advances in System Testing and Validation Lifecycle // View article valid_2013_3_10_40034


Using Filtering to Improve Value-Level Debugging of Verilog Designs

Authors:
Bernhard Peischl
Naveed Riaz
Franz Wotawa

Keywords: hardware/software debugging, model-based debugging, source-level debugging, fault localisation

Abstract:
In this article, we report on novel insights in model-based software debugging of hardware description languages (HDLs). Our debugging model allows one for exploiting failing and passing test cases by incorporating Ackermann constraints. This article reports on an empirical evaluation of the introduced models. The evaluation of our approach on the well-known ISCAS 89 benchmarks concerning single and dual-fault diagno-ses clearly indicates that incorporating passing test cases into fault localization improves considerably the accuracy of the ob-tained diagnosis candidates.

Pages: 49 to 54

Copyright: Copyright (c) IARIA, 2013

Publication date: October 27, 2013

Published in: conference

ISSN: 2308-4316

ISBN: 978-1-61208-307-0

Location: Venice, Italy

Dates: from October 27, 2013 to October 31, 2013

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